Circuit simulation study demonstrates high linearity and ultra-low power in a 16-bit infrared readout converter, highlighting improved thermal imaging sensor performance.
Key Points
To develop a low-power, highly linear 16-bit analog-to-digital converter architecture for large-format infrared focal plane arrays.
Designed a 1024×1024 readout integrated circuit incorporating 12-bit in-pixel pulse frequency modulation ADCs paired with 4-bit column-level single-slope ADCs to reduce quantization noise.
Introduced a pre-comparator to trigger the primary comparator without bias current limitations, cutting propagation delay and shortening the high-power active window.
Evaluated circuit performance using 55 nm CMOS process simulations under a 3.3 V operating voltage and 20 nA illumination conditions.
The pixel unit demonstrated a total power consumption of 0.44 μW under 20 nA illumination and 3.3 V input voltage.
The architecture achieved a low non-linearity error of 0.105% with an extended charge handling capacity of 2.5G e−.