A Simulation Study of SiGe Shell Channel CFET for Sub-2-nm Technology Nodes

In this article, a SiGe shell complementary FET (CFET) composed of an inversion mode (IM) nFET and a junctionless accumulation mode pFET under 2-nm (N2) and 1.5-nm (N1.5) technology nodes was studied for the characteristics of a single device and the CMOS logic circuit using 3-D numerical simulation. A comparison study between Si shell nanosheet and SiGe shell CFET with a Ge mole fraction in the range of 0.5–0.9. Compared with the Si shell nanosheet (NS), the SiGe shell CFET improves the ON-state current, transconductance, transition frequency, and intrinsic delay up to 29%, 32%, 31%, and 21%, respectively. Due to the mobility improvement in SiGe shell CFET, the fall time, rise time, propagation delay, and maximum operating frequency of theSi_0.5Ge_0.5shell CFET are also improved up to 2%, 43%, 3%, and 3%, respectively, compared with their Si shell counterparts. This SiGe shell CFET has a lower parasitic RC, a smaller layout area, and better analog and digital performance at the sub-2-nm technology node. This makes it a promising architecture for future high-performance CMOS logic applications.