Key result
Low-noise CMOS front-end amplifier achieves high gain and common-mode rejection using just 280 μW.
This paper presents a novel low-noise front-end amplifier design suitable for recording small physiological signals such as ECGs.
This paper presents a low-noise front-end amplifier with configurable gain, targeting the recording of small signals, such as the electrocardiogram (ECG) or electroneurogram (ENG). The circuit consists of a continuous-time input stage using lateral bipolar transistors realized in complementary metal-oxide semiconductor (CMOS) technology followed by a switched-capacitor integrating stage. The voltage gain is adjustable by varying the phase delay between two system clocks. Simulated and measured results for a chip fabricated in 0.35-μm CMOS technology are reported. The amplifier occupies an active area of 0.064 mm(2), yields a nominal gain of 630 V/V with more than a 50-dB tuning range, less than 16 nVrms/√Hz input noise and a common-mode rejection of more than 97 dB. Its power consumption is 280 μW with a ±1.5-V supply.
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Robert Rieger (2011) studied this question. Low-noise front-end amplifier with configurable gain was evaluated on Amplifier performance characteristics (gain, noise, common-mode rejection, power consumption). A low-noise front-end amplifier fabricated in 0.35-μm CMOS technology achieved a nominal gain of 630 V/V, <16 nVrms/√Hz input noise, >97 dB common-mode rejection, and 280 μW power consumption.
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