An 8-bit 10 MS/s folding and interpolating ADC using the continuous-time auto-zero technique

An 8-bit 10-MS/s folding and interpolating analog-to-digital converter (ADC) using the continuous-time auto-zero technique is presented. Compared with the conventional architecture, it can improve the nonlinear errors and enhance the signal-to-noise-and-distortion ratio (SNDR). Both architectures have been fabricated on the same die of a 0.35-/spl mu/m DPDM CMOS process and measured under the same conditions with a 2.7-V supply voltage and 10-MHz sampling rate. The continuous-time auto-zero architecture shows an ENOB of 7.7 bits while the conventional one shows 5.8 bits.