BEOL-Compatible MFMIS Ferroelectric/ Anti-ferroelectric FETs—Part II: Mechanism With Load Line Analysis and Scaling Strategy

In Part I, we experimentally demonstrated the back-end-of-line (BEOL) compatible ferroelectric field-effect-transistors (FeFETs) and anti-FeFETs (AFeFETs) with a metal-ferroelectric–metal-insulator–semiconductor (MFMIS) structure, realizing memory window (MW) larger than the theoretical limit of conventional FeFETs. To better understand the device behaviors, a meticulous investigation using load line analysis is presented with consideration of area ratio (AR) and, more significantly, charge trapping effects, and it is the first time that the methodology of FeFET load line analysis has been systematically explained, which stands for an indispensable tool for describing, understanding, and researching related devices. Furthermore, as we find out that a sufficient AR is one of the most critical parameters for the design to take full advantage of the MFMIS Fe/AFeFET, a scaling strategy implementing a channel-all-around (CAA) vertical device is proposed. Through the simulation study, the vertical CAA devices are proved to have a small effective AR intrinsically due to the radius ratio between the inner and outer layers. Meanwhile, they are promising to build the memory array with a 3D-nand-like structure.