Realizing High-Voltage Junction Isolated LDMOS Transistors With Variation in Lateral Doping

High-voltage lateral diffused metal-oxide semiconductor (LDMOS) transistors with a variation in the lateral doping (VLD) of drift regions are demonstrated in junction isolation technology using a fully implanted CDMOS process. The VLD profile is realized by using an analytical approach reported previously. The analytical model is verified through simulations and experiment. Results indicate that higher breakdown voltages can be achieved for a given drift length using a VLD profile in comparison to uniform doping while offering a good tradeoff between breakdown voltage and specific on-resistance.