A GMSK modulator using a /spl Delta//spl Sigma/ frequency discriminator-based synthesizer

This paper describes a new transmitter architecture suitable for wideband GMSK modulation. The technique uses direct modulation of /spl Delta//spl Sigma/ frequency discriminator (/spl Delta//spl Sigma/FD)-based synthesizer to produce the modulated RF signal without any up-conversion. Digital equalization is used to extend the modulation data rate far beyond the synthesizer closed-loop BW. A prototype 1.9-GHz GSM transmitter was constructed consisting of a /spl Delta//spl Sigma/FD-based synthesizer and a digital transmit filter. The synthesizer consists of an 0.8-/spl mu/m BiCMOS /spl Delta//spl Sigma/FD chip, a digital signal processor FPGA, and an off-chip D/A converter, filter, and VCO. Measured results, using 271-kbit/s GSM modulation, demonstrate data rates well in excess of the 30-kHz synthesizer closed-loop BW are possible with digital equalization. Without modulation, the synthesizer exhibits a -76-dBc spurious noise level and a close-in phase noise of -74 dBc/Hz.