An Intrinsically Linear Multi-Rate Continuous-Time Zoom ADC Achieving 97.4-dB DR and 105.7-dB SFDR in 50-kHz Signal Bandwidth

This article presents an intrinsically linear continuous-time (CT) zoom analog-to-digital converter (ADC) architecture that uses a coarse first-order CT delta-sigma modulator (Δ ΣM) followed by a fine third-order CT-Δ ΣM. The 1.5-bit output of the coarse CT-Δ ΣM is filtered by an 8-tap finite impulse response (FIR) filter, and then, a current-steering DAC provides intrinsically linear outputs to the fineΔ ΣM. The associated delay is mitigated by increasing the coarse sampling rate by a factor of 4. The coarseΔ ΣM significantly relaxes the requirements of the fineΔ ΣM, but despite the faster sampling rate, consumes negligible power, because its noise is canceled for the final output, allowing the use of a relatively large input resistor. The ADC prototype fabricated in a 65-nm CMOS process occupies an area of0.124~mm^2and consumes only243~μW from a 1.2-V supply. It achieves 92.0-dB signal-to-noise and distortion ratio (SNDR), 92.3-dB signal-to-noise ratio (SNR), 97.4-dB dynamic range (DR), and 105.7-dB spurious-free DR (SFDR) over a 50-kHz bandwidth without using DAC linearization or calibration. This corresponds to Schreier FoMs of 175.1 dB (SNDR) and 180.5 dB (DR).