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A new device structure and method of fabricating a silicon bipolar transistor is proposed. The device has reduced collector parasitic capacitance and resistance as compared to other advanced bipolar technologies. By using selective and lateral epitaxial overgrowth techniques the buried (N+) layer is not necessary. Two-dimensional computer simulations show theCCS × RCproduct to be reduced by a factor of 5.45 along with reduced CCB.
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G.W. Neudeck (1987) studied this question.
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