Optimization of double metal-gate InAs/Si heterojunction nanowire TFET

The performance of a double metal-gate (DG) InAs/Si heterojunction gate-all-around vertical nanowire tunnel field effect transistor (TFET) is studied using a technology-computer-aided-design tool. Typical drawbacks of the conventional TFET are resolved by taking advantage of using (i) InAs source and (ii) DG structure. The InAs is used as a source material to address the low on-state drive current in the TFET. In addition, a double metal-gate structure is adopted to control the ambipolar current by optimizing the work function of metal gates. Furthermore, the effect of fabrication-induced interface traps at InAs/Si and Si/HfO 2 on device performance is studied. Predictive simulations with various interface traps indicate that a steep subthreshold slope is achieved for D it ⩽ 10 13 cm −2 eV −1 at the InAs/Si interface. To further analyze the optimized device, DC and AC analysis is done for the optimized TFET with traps.