A 12.24-GHz MDLL With a 102-Multiplication Factor Using a Power-Gating-Based Ring Oscillator

This work presents a multiplying delay-locked loop (MDLL) that can generate an ultralow jitter output signal,SOUT, at a very high output frequency,fOUT. Conventional MDLLs are limited in increasingfOUTdue to their series-switch-based multiplexer (MUX) that is used to replace a jittery edge of the ring oscillator (RO) with a clean edge of the reference clock,SREF. To overcome this limitation, the proposed MDLL removes the series MUX and uses a power-gating (PG) technique that periodically turns the RO on and off synchronously toSREF, thereby removing the accumulated jitter ofSOUT. By doing this, the PG-MDLL can achieve an ultralow jitter atfOUTthat is more than 12 GHz with a multiplication factor (N) larger than 100. The PG-MDLL employs a single-pulse generator (SPG) to fill in one missing pulse, while the RO is turned off. Then, to equalize the spacing of all edges inSOUT, which come from either the RO or the SPG, a background calibrator was used to correct various errors by dynamically changing the calibration target. We also proposed an analog-digital-hybrid accumulator (HACC) that can provide both fine resolution and wide bandwidth. This PG-MDLL was fabricated in a 40-nm CMOS technology, and it used an area of 0.066 mm2 and consumed a power of 14.7 mW. At 12.24 GHz ($N =102$), the measured rms jitter and reference spur were 122 fs and −60 dBc, respectively.