This paper describes the design of a CMOS frequency synthesizer targeting wireless local-area network applications in the 5-GHz range. Based on an integer-N architecture, the synthesizer produces a 5.2-GHz output as well as the quadrature phases of a 2.6-GHz carrier. Fabricated in a 0.4-/spl mu/m digital CMOS technology, the circuit provides a channel spacing of 23.5 MHz at 5.2 GHz while exhibiting a phase noise of -115 dBc/Hz at 2.6 GHz and -100 dBc/Hz at 5.2 GHz (both at 10-MHz offset). The reference sidebands are at -53 dBc at 2.6 GHz, and the power dissipation from a 2.6-V supply is 47 mW.
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Lam et al. (2000) studied this question.
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