Reduction of Process Variations for Sub-5-nm Node Fin and Nanosheet FETs Using Novel Process Scheme

Process (systematic) variations of sub-5-nm node fin field-effect transistors (FinFETs) and nanosheet field-effect transistors (NSFETs) were investigated thoroughly using fully calibrated TCAD. All the process parameters consisting of front-endas well as middle-of-line structure were independently randomized within feasible process conditions. A novel process scheme called source/drain patterning (SDP), having a superior performance by decreasing outer fringing capacitance through the downsized source/drain (S/D) epi, has also been analyzed for the variability study. SDP FinFETs have smaller variations of threshold voltages (Vth), OFF-state currents (IOFF), and effective currents (Ieff) than conventional ones because the subfin leakage is effectively controlled by bottom oxide (BO) beneath the source/drain instead of high punch through-stopper doping. The Spearman's correlation results between process parameters, IOFF, and Ieff, showed that the process parameters affecting the short-channel effects vary IOFF and Ieff greatly. Especially, the most critical one was the fin width (Wfin) for FinFETs. SDP NSFETs have the smallest variations of Vth, IOFF, and Ieff. The BO blocks the bottom leakage completely, and the variations of nanosheet(NS)thickness(TNS)are much smaller than those of Wfin due to the different process flows: epitaxial growth for TNS versus patterning for Wfin. Therefore, NSFETs are promising to reducethe variations of Vth, IOFF, and Ieff in the sub-5-nm node.