Efficient FIR Filters Using Precise Application of Algorithmic Level Transformations

In most DSP applications, FIR filters are used as they provide unconditional stability and linear phase characteristics. However, FIR filters require relatively higher numbers of taps in comparison with IIR filters and this may affect the performances in terms of most of the metrics. Developing FIR filter architectures with simultaneous Improvement in throughput and energy efficiency, while minimizing power, area, and latency is always a challenge due to the trade-off between performance metrics. To this end, three variants of high-performance FIR filters are presented. Three levels of modifications including retiming, fine-grain pipelining, and the use of efficient Booth multipliers and adders are incorporated to achieve overall improvement in performances. The CPD, ELT, power, area, PDP, and ADP of the proposed filter FRFIR-5 are reduced by 25.15%, 44.83%, 49%, 65.64%, 57.11%, and 65.52% respectively in comparison with fully flexible retimed filter and by 57.57%, 55.56%, 11.27%, 11.98%, 57.69%, and 49.92% respectively in comparison with retimed filter using modified square root adders and radix-4 modified Booth multipliers. Cadence software with gpdk 45 nm standard cell library is used for the design and implementation.