A precise cyclic CMOS time-to-digital converter with low thermal sensitivity

In this paper, a precise cyclic CMOS time-to-digital converter (TDC) with low thermal sensitivity is proposed. Through compensation, the thermal sensitivity of the new cyclic time-to-digital converter is reduced dramatically. The proposed TDC not only possesses reduced thermal sensitivity but also has a small chip size. The circuit was fabricated with TSMC 0.35 /spl mu/m CMOS technology. The size of the circuit is only 0.40 mm by 0.30 mm. The experimental results show that a /spl plusmn/6% resolution variation of the new TDC was achieved over 0/spl deg/C to 100/spl deg/C temperature range which is much better than the /spl plusmn/25% resolution variation of the original uncompensated version. The effective resolution is as fine as 57.3ps/LSB at room temperature with a fluctuation of /spl plusmn/3.5 ps over 0/spl deg/C to 100/spl deg/C temperature range, and the corresponding integral nonlinearities are all within /spl plusmn/0.8 LSB. The minimum measurement rate is 33 kHz. The measured power consumption is about 3.5 uW.