A 2.16-pJ/b 112-Gb/s PAM-4 Transceiver With Time-Interleaved 2-b/3-b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28-nm CMOS

This article presents a 112-Gb/s four-level pulse amplitude modulation (PAM-4) transceiver (TRX) for extra-short-reach (XSR) applications in 28-nm CMOS. The receiver (RX) adopts a 4 × 6 time-interleaving structure with 2-bit and 3-bit sub-analog-to-digital converters (ADCs) for decoding the PAM-4 signal, eliminating the need for high-speed samplers and saving significant power. The proposed unbalanced baud-rate phase detector (PD) increases the clock and data recovery (CDR) tracking bandwidth without degrading high-frequency (HF) jitter performance. The transmitter (TX) adopts an unsegmented voltage-mode driver with three-tap feed-forward equalizer (FFE). The output impedance control loops maintain the output impedance as different FFE coefficients are applied. This architecture provides high FFE resolution while consuming relatively low power. Designed and fabricated in 28-nm CMOS, the PAM-4 TRX achieves a bit error rate (BER) of-12at 112 Gb/s with 2.16-pJ/b energy efficiency over a channel with 8.5-dB Nyquist loss.