High-performance direct digital frequency synthesizers in 0.25 /spl mu/m CMOS using dual-slope approximation

This paper presents a detailed description of direct digital frequency synthesizers (DDFS) using an optimized piecewise linear approximation for phase to sine mapping, named dual-slope. The dual-slope technique allows reducing ROM size with respect to previously proposed piecewise-linear approximation approaches, with beneficial effects on system performances. Two high-speed DDFS have been fabricated and characterized in 0.25 /spl mu/m CMOS technology. Both circuits produce two quadrature 12 bit outputs with a spectral purity of 80 dBc. The first circuit reaches a maximum operating frequency of 600 MHz by using six pipelining stages. The second circuit operates up to 480 MHz clock speed while dissipating only 72 /spl mu/W/MHz. Analytical investigation of spectral performances achievable by using dual-slope approximation and detailed description of high-speed flip-flop employed in 600 MHz DDFS are also presented in this paper.