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A three-stage bandpass sigma-delta (/spl Sigma//spl Delta/) analog-to-digital converter has been designed specifically for operation at low oversampling ratios. In the proposed architecture, the center frequency of the third stage is shifted slightly from that of the first two stages to achieve more efficient noise shaping across the signal band. An experimental modulator based on the proposed topology has been integrated in a 0.25-/spl mu/m CMOS technology and achieves a dynamic range of 75 dB with a maximum signal-to-noise-plus-distortion ratio (SNDR) of 70 dB when digitizing a 2-MHz signal band centered at 16 MHz. This circuit implements an f/sub s//4 bandpass architecture and thus operates at 64-MHz clock rate. It dissipates 110 mW from a 2.5-V supply, and its active area is 4 mm/sup 2/.
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Tabatabaei et al. (2000) studied this question.
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