Specification-driven EM-aware machine-learning framework for full-circuit synthesis and capacitor-bank optimization of 3–80 GHz LC-DCOs

This work presents a specification-driven, EM-aware machine-learning (ML) framework for full-circuit synthesis and multi-topology capacitor-bank optimization of 3–80 GHz LC Digitally Controlled Oscillators (LC-DCOs) implemented in 22-nm FD-SOI technology. The proposed automation flow maps a performance specification vector, including the required tuning range ( f min , f max ) , frequency resolution, phase-noise constraints, power budget, and output-swing requirements, directly to a complete LC-DCO implementation. To account for layout-dependent electromagnetic and parasitic effects, the underlying dataset incorporates EM-characterized LC-tank components, together with three distinct post-layout RC-extracted switched-capacitor-circuit (SCC) topologies. The ML engine jointly determines the active-core and current-mirror sizing, bias-current selection, inductor geometry, and optimum capacitor-bank configuration. During bank generation, the framework adaptively selects the most suitable SCC topology for each bank, determines the required number of banks and bit allocation, scales the capacitors, and configures either binary-weighted or thermometer-coded control. It further supports both fully digital operation and hybrid tuning architectures employing varactors for fine frequency resolution. The synthesized control codes are verified to ensure monotonic frequency ordering and contiguous coverage of the required tuning range. Validation against circuit-level simulation results demonstrates high fidelity to the target specifications, yielding a mean frequency error below 1.5%, a 95th-percentile phase-noise error below 2.0 dB, and a power-consumption error within 5%, while satisfying all target constraints in 90.5% of the randomized test cases. Once trained, the framework performs surrogate-assisted specification-to-implementation synthesis using bounded candidate search and fixed-bank refinement, reducing time-consuming iterative circuit simulations and manual redesign loops for new specifications.