S ² FAM: Signal-slowdown-based Fault Attack Mitigation Method for Secure Multi-tenant FPGA

Multi-tenant Field-programmable Gate Arrays (FPGAs) in cloud service are vulnerable to remotely exploitable attacks, among which power waster circuit (PWC)-based fault attacks have been demonstrated as a highly feasible one. PWC generates high switching activities and causes a sudden voltage drop in the power distribution network (PDN), resulting in a delay of signal propagation and FPGA malfunction. Existing countermeasures deploy bitstream checking methodologies or deploy numerous on-chip sensors to mitigate voltage-drop attacks. Since new PWCs without combinatorial loops and a multi-source attack are emerging, the current countermeasures lack the ability to mitigate new security challenges in multi-tenant FPGAs. To address these issues, a Signal-slowdown (SS)-based fault attack mitigation (S 2 FAM) method is proposed to detect both combinatorial (ring-oscillator (RO)-based PWC) and non-combinatorial (ring-oscillator Flip-flop (ROFF)-based PWC) loop-based attacks and precisely pinpoint the attack locations. A new calibration technique in S 2 FAM facilitates to identify and remove unstable sensor data, thus significantly reducing false positives. Moreover, the proposed method localizes both the single- and multi-source attacks in the FPGA by utilizing a tenant-level SS ranking (TSSR)-based algorithm. Experimental results show that the proposed method reduces the false alarm by 45.8%, compared to the existing works. Our proposed algorithm for attack localization achieves a 100% success rate and reduces the attack localization area for a multi-source attack by 25.2% than an existing countermeasure. The successful localization is achieved by utilizing our proposed method within 2 \(μ\) s (200 clock cycles) of attack duration. The proposed signal slowdown metric with the calibration process reduces the number of on-chip sensors by 78% and the localization time by 90.5%, compared to the baseline.