Degradation Mechanisms of SiC MOSFET Power Module with Cu-Cu Die Top Interconnects under Power Cycling Stress

Because of the wide application of die top interconnects with Cu bonding wire, the weak points in SiC MOSFET power modules presented a huge difference compared to the conventional modules with Al wire. The lack of understanding of the failure modes and mechanisms has become an obstacle to improving its reliability further. In this paper, the accelerated aging of the SiC MOSFET power module using DTS (Die Top System) was carried out using a power cycling test (PCT). The delamination of the upper sintered Ag layer became the primary failure mode. The Al wire of the Kelvin source was also found burned out. It was verified that imbalanced electric and thermal distribution in different power branches of the multichip paralleled module gradually deteriorated during power cycling by the electrothermal coupling finite element simulation and circuit analysis. Then, the burning of the Kelvin source bonding wires was due to the large circulating current flowing through the Kelvin source bonding wires across different branches. In addition, the chip level degradation of SiC MOSFETs resulting from the package degradation was found. The heat concentration caused the broken interlayer dielectric (ILD) due to the large current flowing through the tail region of the gate bus horizontally.