Thermal coupling effects on the failure behavior of multi-chip parallel SiC power modules with double-sided Cu interconnections

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Multi-chip parallel architecture is widely used in full-bridge power modules for electric vehicles to achieve high current capability. However, the high-power density and compact chip layout intensify thermal coupling, generating lateral temperature gradients that threaten module reliability. This study investigates the failure signatures and interconnect degradation of a multi-chip parallel Silicon Carbide (SiC) module with double-sided copper (Cu) interconnections under power cycling test (PCT). In-situ infrared thermography revealed pronounced thermal coupling, the central chips experienced the highest junction temperatures and failed prematurely. The dominant failure modes included cracking of die-top Cu buffer interconnect, delamination of the die-top electrode metallization, debonding of the die-bottom Cu sintered layer, and lift-off of the Kelvin source wire bonds. Microstructural characterization further revealed spatially non-uniform degradation of the interconnects governed by thermal coupling. Finite element analysis (FEA) was then performed to clarify the origins of these coupling-induced failure modes. The heterogeneous degradation of the die-top and die-bottom interconnects and its influence on electrothermal transport were quantitatively evaluated. Finally, an improved chip layout is proposed to mitigate thermal coupling. The results provide guidance for improving the long-term reliability of high-power SiC modules.