High density fan-out-chip-on-substrate-embedded bridge (FOCoS-Bridge) technology has been successfully built on a large chip module incorporated ten (10) chiplets and ten (10) silicon (Si) bridge dies with more than three times (3X) silicon reticle size. One of the most difficult aspects of this large body size is the chip on substrate (CoS) technique to resolve the larger warpage issue caused by the mismatch in coefficient of thermal expansion (CTE) among various materials from Si dies, redistribution layer (RDL), different molding layers, copper pillar (CuP), Si Bridge, micro bumps to organic substrate.The development of the thermocompression bonding (TCB) technique for chiplet integration on the state-of-the-art FOCoS-Bridge technology is presented in this work. FOCoS-Bridge is an innovative approach to connecting chiplets for high density in high performance computing, artificial intelligence, and machine learning (HPC/AI/ML) applications by incorporating a tiny Si bridge die into a fan-out (FO) organic RDL interposer. In this paper, FOCoS-Bridge platform is implemented on 1 st test vehicle (TV-1) with FO size of 31 x 47 mm 2 and large package size of 70 x 78 mm 2 . Moreover, the second test vehicle (TV-2) is also built with stitching technology and has a more complex backside metallization (BSM) feature with a FO size of 50 x 50 mm 2 and a larger package size of 76.5 × 80 mm 2 . Overall FOCoS-Bridge process flow with BSM, comparison study of traditional mass reflow (MR) and TCB, development of BSM, TCB process flow and bonding profile are also elaborated. Furthermore, the quality of BSM, FO chip module (CM) warpage and the effect of CoS results are also examined by using various methods, such as optical microscope, shadow moiré, x-ray, cross section using focused ion beam (FIB) and scanning electron microscope (SEM) inspection. The results of this work show that both distinct large TVs can be implemented to achieve good solder joint integrity and pass electrical open/short (O/S) test. Finally, the successful validation of reliability tests demonstrates that the fine tune development of TCB method is appropriate for large-scale chiplet integration with embedded Si bridge, leading to high density advanced packaging for high volume manufacturing (HVM).
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Wudjud et al. (2024) studied this question.
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