Research on the Latch-Up Mechanism of DSOI at High Temperature

The latch-up at high temperature is investigated in Double Silicon-on-Insulator (DSOI) devices. Experimental results show the leakage current of both NMOS and PMOS increases with temperature rising, and latch-up occurs at 575 K for NMOS and 525 K for PMOS. Noise decreases with increasing temperature before latch-up, and noise increases dramatically when latch-up occurs. The 1/f noise test indicates that the change in carrier concentration dominates the noise change at room temperature, while at high temperature (575 K) it is affected by carrier concentration and mobility. TCAD simulations show that the band-to-band tunneling effect governs the carrier generation around room temperature and the impact ionization weighs more at high temperatures. Finally, a model for high-temperature latch-up in DSOI devices is developed, which can be used to predict latch-up voltage.