Understanding HZO Thickness Scaling in Si FeFETs: Low Operating Voltage, Fast Wake-Up, and Suppressed Charge Trapping

<tex-math notation="LaTeX">Hf0.5</tex-math> <tex-math notation="LaTeX">Zr0.5</tex-math> <tex-math notation="LaTeX">O₂</tex-math> (HZO)-based ferroelectric field effect transistor (FeFET) has been recognized as a promising nonvolatile memory due to its excellent scalability and CMOS process compatibility. To realize memory operation with low operating voltage, it is essential to gain a systematic understanding of HZO scaling effects, especially under the thickness of HZO <tex-math notation="LaTeX">$<$</tex-math> 10 nm conditions. In this work, we study n-FeFET with HZO thickness ranging from 4.1 to 11 nm and analyze the HZO scaling effects in FeFET. Differing from metal–ferroelectric–metal (MFM) with thin HZO, FeFET with thin HZO shows no strong wake-up effect. Besides, the low-voltage operation, low subthreshold swing (SS) value, and higher current memory window (MW) (or <tex-math notation="LaTeX">I_on</tex-math> / <tex-math notation="LaTeX">I_off</tex-math> ratio) brought by HZO scaling are revealed. Moreover, the lower charge trapping density is observed in FeFETs with HZO thinner than 10 nm and improved read-after-write delay is observed in 5.2-nm FeFET. This work sets up a systematical direction for understanding the scaling impacts of HZO on the electrical characteristics of Si FeFET.