Suppression of Gate-Induced-Drain-Leakage Utilizing Local Polarization in Ferroelectric-Gate Field-Effect Transistors for DRAM Applications

This study proposed a novel approach to enhance the retention characteristics in dynamic random access memory (DRAM) by employing a unique local polarization method, attempting to increase the threshold voltage ( <tex-math notation="LaTeX">V_th </tex-math> ) to reduce subthreshold leakage current while alleviating gate-induced drain leakage (GIDL) current in a ferroelectric gate-field effect transistor with a recessed circular channel. Through the optimization of the position-dependent polarization control along the channel, it is revealed that the polarizations on the source/drain sides can be independently adjusted without interference, resulting in an impressive 80% reduction in GIDL current accompanied by an increase in <tex-math notation="LaTeX">V_th </tex-math> by localized polarizations. Moreover, robustness measurements against temperature variations and read stress confirmed the stable maintenance of locally polarized states, underscoring an effective approach to addressing the performance and reliability limitations of DRAM cell transistors.