FOWLP for Next-Generation Optical Switches: Scalable Packaging Solutions for Photonic-Electronic Integration

The continuous growth of data-driven applications such as 5G fronthaul, memory disaggregation, and autonomous systems demands increasingly efficient and scalable network technologies. Optical switching is emerging as a key solution due to its potential for low-latency operation, high bandwidth, and energy efficiency. However, the integration of photonic and electronic components into compact and manufacturable packages imposes significant challenges, especially at high interconnect densities. This paper presents the development and validation of a fan-out wafer-level packaging (FOWLP) approach as part of the Horizon Europe project PUNCH. The work focuses on demonstrating a scalable and precise process flow capable of integrating multiple dies, including a photonic integrated circuit (PIC) placeholder and several electronic ICs (EICs), into a common package A critical aspect of the PUNCH approach is the development of a scalable, high-performance electrical and optical packaging solution based on a 200 mm FOWLP process. The concept includes a two-layer ERDL with line/spacing of 10/10 μm, allowing short interconnects between PIC and EICs, thereby improving overall performance and reducing power consumption. The package can be connected to a high-density substrate via soldering or substrate embedding. Both approaches are evaluated within PUNCH. For the optical interface, the implementation of an optical redistribution layer (ORDL) is investigated to facilitate scalable fiber coupling, further enhancing the practicality of FOWLP for optoelectronic integration. In this work, we present the first experimental results of a FOWLP demonstrator, where multiple EICs have been integrated with a large central die, resembling the PIC, to assess manufacturability, die placement accuracy, warpage control, and electrical performance.