Physics-based unified analytical model capturing the transport and trapping mechanisms of electrons and holes in GaN-based heterostructures under a high substrate bias

GaN-based high electron mobility transistors are essential for high voltage power-electronic switching applications. The device heterostructure contains various thin film epitaxially grown layers, including an undoped GaN channel, C-doped GaN buffer layer, AlN spacer layer, and p-type Si substrate. Due to the high voltage switching, these devices suffer from severe dynamic performance degradation from charge trapping and de-trapping phenomena at various hetero-interfaces and bulk regions. One of the primary vulnerabilities comes from dynamic on-resistance, in which the device’s on-resistance increases when switched from off-state to on-state during its operation. The increased on-resistance is due to off-state trapping in substrate and surface trapping. While the phenomena are being aggressively studied, various contradicting reports on the degree of adverse effects and physical mechanisms involved exist. Here, we developed a physics-based analytical model that provides a universal framework capturing all the substrate-related trapping mechanisms for GaN-based heterostructures. The substrate ramp and the stored charges in the device are computed as a function of time and substrate voltage using the developed model. The model provides insight into channel-on-resistance dependence on each layer of the device heterostructure. This model can be a pathway to designing heterostructures and addressing the on-resistance degradation problem to develop highly efficient GaN devices.