Key result
FPGA-based DWT-ADTF hardware effectively denoises ECG signals in real-time for continuous monitoring.
Why the study?
Hardware, time, and power consumption remain challenging in embedded ECG filtering systems due to the high computational complexity of filtering algorithms.
A novel embedded hardware architecture using DWT-ADTF on an FPGA provides effective, real-time ECG signal denoising.
Numerous are the embedded systems that have been suggested to filter the ECG signal from the noises that get added during its recording. However, hardware, time, and power consumption are still challenging because of the high computational complexity of the considered algorithms. The DWT-ADTF is a recent low-complexity technique that has shown its efficiency and effectiveness against ECG noises. This paper presents a high-quality and real-time embedded architecture for denoising ECG signal. The system consists of a hardware architecture implemented in the Cyclone V DE10 FPGA. The denoising quality assessment is based on the MIT-BIH arrhythmia and variant noise types for variant input SNR values. The effectiveness of our embedded system is evaluated through the RMSE and SNR out. The proposed architecture provides significant results that convinces its suitability for real-time ECG monitoring systems.
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Bendahane et al. (2026) studied this question. An FPGA-based embedded hardware architecture utilizing the DWT-ADTF technique effectively denoises ECG signals in real-time, demonstrating suitability for continuous ECG monitoring.
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