Low-frequency and low-power NIOS-V soft-processor based system-on-chip architecture for real-time ECG signal denoising using the DWT-ADTF process

Several are the embedded architectures that have been introduced to filter ECG signals. However, processing frequencies, consumed hardware, power, and time are still challenging. The elevated computational complexity of the considered algorithms is the major reason. The DWT-ADTF is a recent low-computational complexity process that has been introduced for ECG denoising. This paper proposes an FPGA-based software architecture providing real-time ECG signal filtering with low frequency and power consumption. Our system consists of a Nios-V soft processor interconnected to 69.34 KB of RAM through the AXI4 and Avalon interfaces. The Nios-V is used thanks to its hardware flexibility and five-stage pipeline. Using the C language, our architecture is designed to take advantage of this hardware capacity. The data is loaded and treated through a sample-by-sample and shifting approach. Consequently, the processor’s pipeline is well-derived for real-time processing, and no permanent data storage is needed. Thus, under only 50 MHz, our architecture ensures real-time data loading and processing while consuming less hardware and power. The denoising quality is assessed using the average MSE, PRD, and SNRimp. Several noise types and ECG signals from the MIT-BIH Arrhythmia database are involved. The processing frequency and the consumed hardware, power, and time evaluate the efficiency and performance of our architecture. Promising results are achieved compared to other works, which makes our architecture appropriate for real-time ECG monitoring systems. Further, its lower consumption favors more ECG processing integration.