Key result
Hybrid FPGA architecture for ECG denoising achieves ~0.3 ms processing time using minimal hardware registers.
Why the study?
ECG signals are affected by physiological and technical noises that deteriorate morphology, requiring real-time high-performance embedded architectures for complex preprocessing filtering techniques.
The proposed FPGA architecture enables efficient, real-time ECG signal denoising with minimal hardware resource requirements.
May enable real-time ECG denoising in embedded devices; leaves open clinical validation before adoption.
The ECG signal, like all signals obtained when instrumenting a data acquisition system, is affected by noises of physiological and technical sources such as Electromyogram (EMG) and power line interferences, which can deteriorate its morphology. To overcome this issue, it’s subjected to apply a preprocessing step to remove these noises. Filtring techniques are complex computations becoming more common in medical applications, which must be completed in real-time. As a result, these applications are geared at integrating high-performance embedded architectures. This paper presents an FPGA (Field Programmable Gate Array) embedded architecture designed for an ECG denoising hybrid technique based on the Discrete Wavelet transform (DWT) and the Adaptive Dual Threshold Filter (ADTF), dedicated to handle with noises affecting ECG signals. The architecture was designed following a hardware-software codesign using a high-level description language and synthetized to be implemented on different FPGAs due to the structural description flexibility. The global architecture was divided into a set of functional blocks to allow parallel processing of ECG data. The simulation results confirm the high performance of the system in noise reduction without affecting the morphology of the signal. The process takes 0.3 ms with an acquisition frequency of 360 Hz. The whole architecture requires a small area in different FPGAs in terms of resources utilization. It uses less than 1% of the total registers for all FPGA devices which represents a total of 292 registers for Cyclone III LS, Cyclone IV GX, Cyclone IV E, and Arria II GX; and a total of 329 registers for Cyclone V. The logic elements occupancy varies between 3% using Cyclone V and 60% using Cyclone IV GX freeing up space for other parallel processing tasks.
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Mejhoudi et al. (2021) studied ECG signal noise. FPGA embedded architecture for ADTF and DWT hybrid technique vs. ADTF alone or DWT alone was evaluated on Processing time and hardware resource utilization. The proposed FPGA architecture for ECG signal denoising using a hybrid ADTF and DWT technique achieved a processing time of 0.3 ms at 50 KHz and utilized less than 1% of total registers across multiple FPGA devices.
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