The Hardware-Architecture Design of a Hybrid DWT–ADTF-Based Real-Time ECG-Denoising System: An Optimized FPGA Implementation

Electrocardiogram (ECG) signals are highly susceptible to various types of noise, including power-line interference, electromyographic activity, motion artifacts, and baseline drift, all of which compromise diagnostic reliability. Although software-based denoising approaches have the potential for high performance, their computation cost and power requirements, and their nondeterministic execution are not suitable for the stringent real-time and power requirements in embedded and wearable systems. Such limitations restrict the practical applicability of computationally intensive denoising and highlight the need for hardware designs to support the required performance in long-duration monitoring systems. To address these limitations, this work introduces a hardware-efficient ECG-signal-denoising architecture based on the hybrid DWT–ADTF algorithm, which has been selected for its favorable trade-off between low algorithmic complexity and high denoising performance. The proposed design employs a fully pipelined structural-RTL architecture with dual-clock synchronization and memory-aware buffering to ensure deterministic real-time throughput under embedded constraints. The architecture is prototyped on an Intel Cyclone V SoC FPGA environment, which is used as a validation platform. Across multiple noise conditions, the proposed architecture consistently improves signal quality; for instance, using MIT-BIH records with additive white Gaussian noise at 5 dB, the system achieves an SNR improvement of 9.23 dB to 10.00 dB and a PRD of approximately 18%, with 1.09 ms system latency, 426 mW power consumption, and under 5% logic utilization. These results demonstrate the suitability of the proposed architecture for low-power, real-time biomedical monitoring devices.