Design Tradeoffs for an Embedded OpenGL-Compliant Hardware Rasterizer

This is the authors' abstract. We don't add key points for this paper.

Abstract—This paper addresses design trade-offs for lowpower, low-cost embedded 3D graphics accelerators. More in particular it focuses on a low-cost reciprocation hardware algorithm suitable to be implemented in their datapath. The algorithm exploits the limitations of the human visual system that allows a reasonable amount of error to be introduced in the computation process without inducing noticeable artifacts in the final computer-generated image. In the example given in the paper, excerpted from the antialiasing datapath of an embedded QVGA graphics hardware accelerator, for a 14-bit operand, the reciprocal implementation requires an inexpensive operand prescaler, one 1k lookup table with 10-bit entries, and a 5-bit adder, for a maximum relative error of the result of only 1.5 % over the entire range of the operand. Hardware synthesis in a typical 0.18µm process technology has indicated that the hardware implementation requires only 1600 standard cells to achieve a latency of only one clock cycle for a clock frequency of 250MHz. Keywords—graphics architecture; embedded systems; reciprocal approximation; system-on-chip; hardware/software co-simulation I.