A high-efficiency unified matrix processor with low-complexity implicit EVD for Wi-Fi MU-MIMO

To address the rigorous demands of next-generation Wi-Fi MU-MIMO systems characterized by ultra-wide bandwidths, this paper presents a high-efficiency unified matrix processor tailored for Wi-Fi station devices. By leveraging a reconfigurable parallel-pipelined architecture and a novel low-complexity implicit eigenvalue decomposition (EVD) algorithm designed for beamforming feedback, the proposed design efficiently integrates multiple MU-MIMO tasks, including MIMO detection, precoding, and beamforming feedback, within a single core. This unified approach eliminates hardware redundancy inherent in traditional discrete implementations. Implementation results in 28nm CMOS technology show that the proposed processor requires only 140 kGE at 320 MHz. Furthermore, with a high throughput of 160 MMatrices/s for beamforming feedback, the proposed architecture exhibits superior hardware efficiency, providing a scalable solution for high-performance Wi-Fi chips.