A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay

A 256-Mb SDRAM (245.7 mm/sup 2/) has been developed using (1) a high cell occupation ratio (60.2%) array design for chip size reduction and a high yield, (2) a prefetched pipeline scheme (PPS) using a first-in first-out (FIFO) buffer with parallel serial converter for 250-MHz clock frequency operation, and (3) a synchronous mirror delay (SMD) circuit for 2.5-ns clock access and low standby current.