A SLM-based overlay architecture for fine-grained virtual FPGA

FPGA overlay technologies have been introduced to provide inter-FPGA bitstream compatibility by implementing virtual FPGA (vFPGA) layers on physical devices. Conventional LUT-based finegrained vFPGAs have very large resource overheads. In this paper, we propose a fine-grained vFPGA overlay architecture that employs our previously proposed scalable logic module (SLM) as a logic cell. SLMs can cover most frequently used logics with far fewer hardware resources than LUTs. Evaluation results show that a 7-input SLM-based vFPGA can reduce LUT and flip-flop resource usage by up to 32% and 35% on an Artix-7 FPGA, 30% and 35% on a Kintex-7 FPGA, and 30% and 35% on a Kintex UltraScale+ FPGA respectively, as compared to a LUT-based vFPGA of the same input size.