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November 1, 1985IEEE Transactions on Electron Devices

Buried p-layer SAINT for very high-speed GaAs LSI's with submicrometer gate length

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Authors

KYK. YamasakiHiroshima UniversityNKNaoki KatoJikei University School of MedicineMHM. HirayamaNTT (Japan)

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Cite This Study

Yamasaki et al. (1985) studied this question.

synapsesocial.com/papers/6a7cdc9e4fd5c1e90ea1e3cehttps://doi.org/10.1109/t-ed.1985.22289
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Also Consider

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  1. 1GaAs MESFETs with a buried p -layer for large-scale integration1984 · 19 citations
  2. 2Orientation effect reduction through capless annealing of self-aligned planar GaAs Schottky barrier field-effect transistors1983 · 18 citations
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  4. 4Self-align implantation for <i>n</i> <sup>+</sup> -layer technology (SAINT) for high-speed GaAs ICs1982 · 72 citations
  5. 5Influence of n<sup>+</sup>-layer-gate gap on short-channel effects of GaAs self-aligned MESFET's (SAINT)1983 · 20 citations