Negative Bias and Illumination Stress Induced Electron Trapping at Back-Channel Interface of InGaZnO Thin-Film Transistor

Double-sweeping gate voltage mode and positive gate pulse mode were used to investigate the mechanism of negative bias and illumination stress (NBIS) induced hysteresis in bottom-gate InGaZnO TFTs. Threshold voltages (V th ) in reverse measurement shifted positively and were well fitted to a stretched-exponential equation under various gate bias stress conditions. “Hump” effect appeared in the forward measurement and hysteresis gradually increased with stress time. The results indicate that trapped electrons at back interface, trapped holes at front interface and the generation of donor-like states in IGZO bulk channel were reasons for instability of IGZO TFTs under NBIS.