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August 25, 2009IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Parallel Interleavers Through Optimized Memory Address Remapping

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Abstract

This work presents mathematical models and collision-free exchange rules for a parallel interleaver, using which it develops an optimized memory address remapping (OPMM) scheme that enables a classic interleaver to be exchanged for a parallel interleaver readily and efficiently. Both analytic and experimental results demonstrate that the rate of annealing achieved using the OPMM approach is much faster than that achieved using the traditional memory address remapping (MM) method.

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Jing-ling Yang (2009) studied this question.

synapsesocial.com/papers/6a833f64be60e97fec18f508 https://doi.org/10.1109/tvlsi.2009.2019076

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