Verilog-A model of the impurity freeze-out in LDD regions at cryogenic temperatures

This is the authors' abstract. We don't add key points for this paper.

The article shows the practical implementation of the impurity freeze-out effect in the lightly-doped areas of the drain and source (LDD) in the Verilog-A model of the resistor. This model is based on a theoretical understanding of the freeze-out effect at cryogenic temperatures and data from the TCAD simulation of a MOSFET. The TCAD simulation data were represented by transconductance characteristics of n- and p-channel transistors Id(Vg) in linear mode (Vd=0.1 V) at temperature range from -200 °C to 27 °C for transistors with dimensions 10 um × 10 um. The model is applicable to the use as part of a macromodel of a MOSFET transistor for a CMOS bulk process with a supply voltage of 1.8 V and a minimum channel length of 0.18 um. Since the model is based on a limited set of TCAD modeling data, this version is the basis on which it is possible to build a geometrically scalable model that will be valid over the entire range of drain voltages.