A capacitor technology developed to obtain extremely thin Ta/sub 2/O/sub 5/ dielectric film with an effective SiO/sub 2/ film thickness down to 3 nm (equivalent to 11 fF/ mu m/sup 2/) for a 1.5-V, low-power, high-density, 64-Mb DRAM is discussed. The Ta/sub 2/O/sub 5/ has low leakage current, low defect density, and excellent step coverage. The key process is two-step annealing after the deposition of the film by thermal chemical vapor deposition (CVD). The first step involves ozone (O/sub 3/) annealing with ultraviolet light irradiation, which reduces the leakage current. The second step is dry oxygen (O/sub 2/) annealing, which decreases the defect density. A more significant reduction in the leakage current is attained by the combination of the two annealing steps.>
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Shinriki et al. (1989) studied this question.
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