Negative-Bias Temperature Instability of p-GaN Gate GaN-on-Si Power Devices

This is the authors' abstract. We don't add key points for this paper.

The threshold voltage (Vₜₕ) of p-GaN GaN-on-Si power devices has been examined under negative-bias temperature instability (NBTI) stress conditions, and the physical mechanisms are evaluated using 2D device simulation and experimental data. Three regimes ofVₜₕshift (Δ Vₜₕ) as a function of stress time and voltage magnitude at elevated temperatures have been investigated. Under the low gate stress condition, negativeΔ Vₜₕfollows the power-law characteristics resulting from the electron de-trapping/injection process from the p-GaN region to the channel. Under the mid-stress condition, a bidirectionalΔ Vₜₕwas recognized due to spill-over electrons into the p-GaN gate from the channel. At high gate stress, the hole accumulation at the interface between the Schottky contact and p-GaN is responsible for the negativeΔ Vₜₕ.