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A linear power amplifier (PA) is proposed for EDGE application in cellular and PCS bands, using a standard 0.18 μm CMOS technology. The linear PA is adaptively biased according to its power level to efficiently enhance AM-AM characteristics. Nonlinear gate-drain capacitance (C gd) of power transistors, which is one of the major sources of AM-PM nonlinearity, is effectively linearized by adding an additional capacitor in series. The prototype CMOS PA achieves power added efficiencies of 22% and 23% at output powers of 28.5 dBm and 27.5 dBm, at 870 MHz and 1.8 GHz, respectively. The proposed PA meets the class E2 power requirement satisfying error vector magnitude (EVM) and adjacent channel power ratio (ACPR) specifications with EDGE modulated signals.
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Kim et al. (2014) studied this question.
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