A new analytical approach to estimate the effects of SEUs in TMR architectures implemented through SRAM-based FPGAs

In order to deploy successfully commercially-off-the-shelf SRAM-based FPGA devices in safety- or mission-critical applications, designers need to adopt suitable hardening techniques, as well as methods for validating the correctness of the obtained designs, as far as the system's dependability is concerned. In this paper we describe a new analytical approach to estimate the dependability of TMR designs implemented on SRAM-based FPGAs that, by exploiting a detailed knowledge of FPGAs architectures and configuration memory, is able to predict the effects of single event upsets with the same accuracy of fault injection but at a fraction of the fault-injection's execution time.