In this paper, an accurate compact model based on physical mechanisms for dual-gate bilayer graphene FETs is presented. This model is developed based on the 2-D density of states of bilayer graphene and is implemented in Verilog-A. Furthermore, physical equations describing the behavior of the source and drain access regions under back-gate bias are proposed. The accuracy of the developed large-signal compact model has been verified by comparison with measurement data from the literature.
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Aguirre‐Morales et al. (2015) studied this question.
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