Answers are grounded in this paper and cite their sources.
A detailed experimental investigation of single-event upset (SEU) in static RAM (SRAM) chips fabricated using a family of high-performance NMOS (HMOS) depletion-mode-load process technologies, has been done. Empirical SEU models have been developed with the aid of heavy-ion data obtained with a three-stage tandem van de Graaff accelerator. The results of this work demonstrate a method by which SEU may be empirically modeled in NMOS integrated circuits.
No takes yet. Share an insight, caveat, or question.
Zoutendyk et al. (1986) studied this question.
Synapse has enriched 5 related papers. Consider them for comparative context: