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The combined effect of the spacing between adjacent drain junctions, epilayer thickness, and resistivity in VDMOS transistors on both its breakdown voltage andRₒₙ · Aproduct is investigated. It is shown that an increase in the breakdown voltage results as the junctions spacing is reduced. That gives a significant difference in theRₒₙ · Aproduct when compared with results where this effect is ignored. A design optimization study is carried out to determine the parameters of a VDMOS transistor at 1000-V breakdown.
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M. Darwish (1984) studied this question.
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