Key result
Proposed ECG recording front-end achieves low noise and distortion while consuming ~8.5 μW.
The proposed ECG recording front-end achieves low power consumption and low noise, making it potentially suitable for continuous ECG monitoring applications.
May enable continuous ECG monitoring in wearables; leaves open clinical validation of the front-end.
An ECG recording front-end with a continuous- time asynchronous level-crossing analog-to-digital converter (LC-ADC) is proposed. The system is a voltage and current mixed-mode system, which comprises a low noise amplifier (LNA), a programmable voltage-to-current converter (PVCC) as a programmable gain amplifier (PGA) and an LC-ADC with calibration DACs and an RC oscillator. The LNA shows an input referred noise of 3.77 μVrms over 0.06 Hz-950 Hz bandwidth. The total harmonic distortion (THD) of the LNA is 0.15% for a 10 mVPP input. The ECG front-end consumes 8.49 μW from a 1 V supply and achieves an ENOB up to 8 bits. The core area of the proposed front-end is 690 ×710 μm2, fabricated in a 0.18 μm CMOS technology.
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Li et al. (2014) studied this question. ECG recording front-end with continuous-time level-crossing sampling was evaluated on Device performance metrics (noise, THD, power consumption, ENOB). The proposed ECG recording front-end achieved an input referred noise of 3.77 μVrms, 0.15% THD, and consumed 8.49 μW from a 1 V supply with an ENOB up to 8 bits.
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