Three dimensional (BA, SR) TIO 3 stack capacitors for dram application

Three dimensional integration of BSTO thin films for Gigabit DRAM application is performed by a MOCVD BST process combined with a high temperature barrier stack of TaSiN/Ir/IrO2 with SiO2 sidewall protection. The SiO2 layer is formed by a new low temperature HDP process. This barrier stack enables the use of a new two step high temperature MOCVD BST process, which results in high quality BST films. First, a very thin BST seed layer is deposited at 450°C. The second layer is formed at 640°C. Using these two key processes, we have established a baseline for BST capacitors on 0.2μm feature size. 256k capacitor arrays show capacitance up to 18.1 fF/cell with excellent leakage current around 1 fA/cell (DC, 1V). The capacitance is scaling with different capacitor arrays (4k to 256k).