A 10‐b 5‐GS/s Passive T/H Assisted Time‐Interleaved Pipelined‐SAR ADC With Pre‐Quantization and Background Offset Calibration

This letter presents a 10‐bit 5‐GS/s time‐interleaved (TI) pipelined successive‐approximation‐register (SAR) analogue‐to‐digital converter (ADC). By utilizing a full‐speed passive track‐and‐hold circuit (T/H), pre‐quantization can be performed in parallel, alleviating the timing constraint in the first stage. The chopped switches in the passive T/H enable input‐independent background offset calibration for comparators and residue amplifiers. Fabricated in a 28‐nm CMOS process, the prototype ADC achieves 51.8‐dB SNDR and 67.9‐dB SFDR at the Nyquist input.